gerardo_urrea
New member
Hello everyone,
Recently I´ve implemented an ADC Verilog language interface for FPGAs in Digilents Nexys3 development board.
The ADC is the PmodAD1 also from Digilent. It has two 12 bit AD7476 Analog Devices ADCs in it.
This ADC converts 0 - 3.3 volts in 12 bits resolution wich means:
12'b000000000000 = 12'd0 = 0 v
12'b111111111111 = 12'd4095 = 3.3 v
It works fine except for the voltaje representation coming out the FPGA. I already simulated code in ISE Xilinx and nothing
sims to be wrong with it.
What happens is that from 0 to 1.65 v I have 0 - 4095 at the output and from 1.65 to 3.3 I have, again, 0 - 4095 v.
Any idea on what could be going on here?
Recently I´ve implemented an ADC Verilog language interface for FPGAs in Digilents Nexys3 development board.
The ADC is the PmodAD1 also from Digilent. It has two 12 bit AD7476 Analog Devices ADCs in it.
This ADC converts 0 - 3.3 volts in 12 bits resolution wich means:
12'b000000000000 = 12'd0 = 0 v
12'b111111111111 = 12'd4095 = 3.3 v
It works fine except for the voltaje representation coming out the FPGA. I already simulated code in ISE Xilinx and nothing
sims to be wrong with it.
What happens is that from 0 to 1.65 v I have 0 - 4095 at the output and from 1.65 to 3.3 I have, again, 0 - 4095 v.
Any idea on what could be going on here?